Senior Asic Physical Design Engineer

Responsible for physical verification, signal integrity, power integrity, timing closure.
Analyze reports and utilize scripting techniques to develop insights and drive rapid timing closure.
Develop and maintain methodology and flows related to PnR.
Responsible for 1 block or multiple blocks in the project from floorplan to tape-out.
Communicate with customers and others team for technical related issue and input/output requirement.

Benefits: Health insurance, social insurance, and extended insurance packages.
Compensation and Bonus: Competitive salary and performance-based bonuses.
Working Environment: Modern, professional working environment that supports personal development.
Professional Development: Opportunities to participate in specialized training courses, seminars and conferences.
Flexible Policy: Flexible working policy, balance between work and personal life.

Familiarity with all aspects of PnR of high-performance, mixed-signal SoCs in advanced process technology nodes (28nm and below).
Experience on Synopsys or Cadence flow – ICC, Fusion, Innovus, PrimeTime, Formality, Calibre.
At least 3+ years hands-on experience in ASIC physical design including floorplan, power planning, placement, clock tree synthesis, routing, timing, and signal integrity.
Has knowledge of the full design cycle from RTL to GDSII, including chip level.
Proficient in scripting languages (Shell, Tcl and Perl).
Strong communication skills are a pre-requisite as the candidate will interface with a lot of different groups.
Nice to have:
Good knowledge in digital design techniques and the state-of-the-art physical design methods.
Solid fundamentals in IC design flow and ASIC concepts.